Field effect transistor and method for producing a field effect transistor

ABSTRACT

The invention relates to a field effect transistor with a drain region, a source region, a channel region and a gate region. The gate region is provided with a metal layer.

[0001] The invention relates to a field-effect transistor and to aprocess for fabricating a field-effect transistor.

[0002] A field-effect transistor of this type and a process for itsfabrication are known from [1].

[0003] Furthermore, it is known, in the case of the conventionalfield-effect transistor described in [1], that the length of the spacecharge region and, by association, the length of the channel region dare indirectly proportional to the root of the doping of thesemiconductor used as substrate in the field-effect transistor.

[0004] Therefore, the following relationship applies to the field-effecttransistors which are known from [1]: $\begin{matrix}{d \propto \sqrt{\frac{1}{N}}} & (1)\end{matrix}$

[0005] It is clear from this relationship between the length of thechannel region and the doping of the substrate that the scalability of asemiconductor component, in particular a semiconductor field-effecttransistor, is restricted by the fact that the doping of thesemiconductor used can only be scaled to a limited extent.

[0006] Furthermore, [2] describes what is known as a metal tunneltransistor, in which a barrier layer, through which electric chargecarriers are to tunnel and which according to [2] consists of niobiumoxide, is provided between the source region and the drain region of thefield-effect transistor.

[0007] It is described in [3], [4], that what is known as a field effectcan be observed in the metal layer in the case of a very thin metallayer with a thickness of a few nanometers, in particular a thickness of5.5 nm.

[0008] The invention is based on the problem of describing afield-effect transistor and a process for fabricating a field-effecttransistor with a scalability which is improved compared to that of theknown field-effect transistors.

[0009] The problem is solved by the field-effect transistor and theprocess for fabricating a field-effect transistor having the featuresdescribed in the independent patent claims.

[0010] A field-effect transistor has an electrically nonconductivesubstrate, a drain region and a source region.

[0011] Both the drain region and the source region may contain a metalelectrode.

[0012] Between the drain region and the source region there is a channelregion, the channel region having a metal layer, i.e. a metal layerobviously forms the channel region which is required in a field-effecttransistor in order to transfer electrical charge carriers from thesource region to the drain region.

[0013] Furthermore, there is a gate region, by means of which thechannel region can be controlled.

[0014] A field-effect transistor of this type can be produced using thefollowing process.

[0015] A drain region and a source region are formed on or in asubstrate. A channel layer, which forms a channel region, is applied tothe substrate between the drain region and the source region. Aseparating layer is applied to the metal layer and between the drainregion and the source region. A gate region is formed on the separatinglayer, the gate region being electrically separated from the drainregion, the source region and the channel region by the separatinglayer, in such a manner that the channel region can be controlled bymeans of the gate region.

[0016] Evidently, the invention can be regarded as consisting in thefact that the channel region, which in conventional field-effecttransistors is formed by a semiconductor material and can be controlledby means of a gate region, according to the invention is formed by ametal layer which, on account of a field-effect which occurs with a thinmetal layer, can be controlled by means of the gate region of afield-effect transistor.

[0017] A second gate region may be provided in the field-effecttransistor, so that what is known as a dual gate arrangement is formedin the field-effect transistor. The second gate region can also be usedto control the channel region, as in a conventional field-effecttransistor. The first gate region and the second gate region may beelectrically coupled to one another.

[0018] The metal layer may have one or more layers of metal atoms.

[0019] Particularly in view of the very high scalability of the metallayer and the fact that the width of the channel region is independentof the doping of the semiconductor material, since metal is now used toproduce the channel in the field-effect transistor, the scalability ofthe field-effect transistor according to the invention is now improvedconsiderably.

[0020] A further advantage of the invention is to be seen in particularin the high electrical conductivity of the metal layer which forms thechannel region.

[0021] In this way, the power loss which is generated when thefield-effect transistor switches from a first state into a second stateis reduced. On account of the high conductivity of the metal layer, thespeed of the switching operation of the field-effect transistor is alsoincreased considerably compared to conventional field-effecttransistors.

[0022] The metal layer may contain at least one of the following metals:

[0023] platinum, gold, silver, titanium, tantalum, palladium, bizmuth,indium, chromium, vanadium, manganese, iron, cobalt, nickel, yttrium,zirconium, niobium, molybdenum, technetium, hafnium, tungsten, or analloy of at least two of the abovementioned metals.

[0024] The separating layer may be an electrically insulating separatinglayer and/or a layer with a high dielectric constant and/or aferroelectric layer.

[0025] In particular, the separating layer may contain SBT, silicondioxide and/or BST.

[0026] Furthermore, it is provided, according to a configuration of theinvention, for the drain region and/or the source region and/or the gateregion to include metal, for example a metal electrode.

[0027] The metal used for the metal electrode or the metal electrodesmay be the same metals as for the metal layer, i.e. the metal electrodeor the metal electrodes may contain:

[0028] platinum, gold, silver, titanium, tantalum, palladium, bismuth,indium or an alloy of at least two of the abovementioned metals.

[0029] However, it is also possible to use other metals as metalelectrodes.

[0030] On account of the high conductivity of the correspondingconnections, i.e. electrodes, of the field-effect transistor, theoverall conductivity of the field-effect transistor is increased furtheraccording to this configuration of the invention, thus increasing thespeed when the field-effect transistor switches from a conductive stateto a blocking state.

[0031] On account of the high switching speed, the field-effecttransistor is therefore particularly suitable for high-frequencyapplications.

[0032] The drain region and the source region may be formed on thesubstrate in a known way, for example by means of predeterminable dopingof charge carriers, electrons or holes.

[0033] The metal layer may be applied by means of a suitable chemicalvapour disposition process (CVD process), a physical vapour depositionprocess, a sputtering process or an atomic layer deposition process.

[0034] The above-described configurations of the invention with regardto the field-effect transistor also apply to the process for fabricatingthe field-effect transistor.

[0035] Exemplary embodiments of the invention are illustrated in thefigures and are described in more detail below. In the drawing:

[0036]FIG. 1 shows a cross section through a field-effect transistoraccording to a first exemplary embodiment of the invention;

[0037]FIG. 2 shows a cross section through a field-effect transistoraccording to a second exemplary embodiment of the invention;

[0038]FIG. 3 shows a cross section through a field-effect transistoraccording to a third exemplary embodiment of the invention.

[0039]FIG. 1 shows a field-effect transistor 100 according to a firstexemplary embodiment of the invention.

[0040] The field-effect transistor 100 has a substrate 101 comprisingelectrically nonconductive material, i.e. an electrically insulatingmaterial, specifically, according to the first exemplary embodiment,comprising silicon dioxide SiO₂ or aluminium oxide Al₂O₃.

[0041] A first metal electrode 102 and a second metal electrode 103 areapplied to the substrate 101, at a distance of 1 nm to 1000 nm from oneanother, by means of a CVD process, a sputtering process or a physicalvapour deposition process.

[0042] The first metal electrode 102 and the second metal electrode 103may be fabricated from platinum or from titanium. Alternatively, it ispossible to use any desired metal alloys or metals to form the firstmetal electrode 102 or the second metal electrode 103.

[0043] The first metal electrode 102 serves as source region of thefield-effect transistor 100, and the second metal electrode 103 servesas drain region of the field-effect transistor 100.

[0044] A monoatomic or multiatomic metal layer 104 comprising platinumis deposited between the first metal electrode 102 and the second metalelectrode 103 by means of a suitable CVD process.

[0045] The metal layer 104 is electrically coupled to the first metalelectrode 102 and to the second metal electrode 103 and evidently formsa channel region inside the field-effect transistor 100.

[0046] The first metal electrode 102 and the second metal electrode 103each have a width b, in each case symbolically indicated in FIG. 1 by adouble arrow 105, 106, of from 1 nm to 100 nm. In this context, itshould be pointed out that the widths of the metal electrodes 102, 103do not have to be identical.

[0047] The channel region, i.e. the metal layer 104, has an area of 1×1nm² to 1000×1000 nm².

[0048] In a further process step, an electrically insulating separatinglayer 107 of silicon dioxide or silicon nitride Si₃N₄ is applied to themetal layer 104 by means of a CVD process, a sputtering process or aphysical vapour deposition process.

[0049] A gate electrode 109, which forms a gate region, is introducedinto or applied to the separating layer 107 at a distance p from thesurface of the channel region, i.e. from the surface of the metal layer104, as symbolically indicated in FIG. 1 by a further double arrow 108,in a range from 1 nm to 50 nm.

[0050] The gate electrode 109 may also be fabricated from theabovementioned metals or metal alloys from which the first metalelectrode 102 or the second metal electrode 103 may be formed.

[0051] Furthermore, in a final step aimed at protecting the field-effecttransistor 100, a further insulating layer 110, which includes, forexample, silicon dioxide or silicon nitride, is applied above theseparating layer 107.

[0052]FIG. 2 shows a field-effect transistor 200 according to a secondexemplary embodiment of the invention.

[0053] Elements of the field-effect transistor 200 according to thesecond exemplary embodiment which are identical to the elements of thefield-effect transistor 100 according to the first exemplary embodimentare denoted by the same reference numeral.

[0054] The field-effect transistor 200 according to the second exemplaryembodiment is substantially identical to the field-effect transistor 100according to the first exemplary embodiment.

[0055] Therefore, the fabrication processes and the selected dimensionsfor fabrication of the field-effect transistor 200 are also identical tothose of the field-effect transistor 100 as described in connection withthe first exemplary embodiment.

[0056] The field-effect transistor 200 in accordance with the secondexemplary embodiment differs from the field-effect transistor 100 inaccordance with the first exemplary embodiment in particular in that afurther gate electrode 201 is provided in the substrate 101 as the gateregion, referred to below as the second gate electrode 201.

[0057] The first gate electrode 109 is electrically coupled to thesecond gate electrode 201, which is arranged beneath the channel region104 and is at a distance of from 1 nm to 50 nm, as diagrammaticallyindicated by an arrow 203 in FIG. 2, from a lower surface 202 of thechannel region 104.

[0058] This means that, when the first gate electrode 109 is energised,i.e. when an electric potential is applied to the first gate electrode109, a corresponding electric potential is also applied to the secondgate electrode 201.

[0059] Evidently, therefore, the first gate electrode 109 and the secondgate electrode 201 form what is known as a dual gate arrangement in thefield-effect transistor 200.

[0060] According to this exemplary embodiment, the second gate electrode201 is embedded in the substrate 101 using a dual damascene process.

[0061] This means that the structure for the second gate electrode 201is etched into the substrate 101, and then the metal from which thesecond gate electrode 201 is to be formed is deposited in such a mannerthat the structure which is etched for the second gate electrode 201 isat least completely filled with the deposited metal. Any metal whichprotrudes above the structure is removed by means of a chemicalmechanical polishing process (CMP process). This is followed, onceagain, by suitable deposition of the desired oxide.

[0062]FIG. 3 shows a field-effect transistor 300 according to a thirdexemplary embodiment of the invention.

[0063] The field-effect transistor 300 according to the third exemplaryembodiment substantially corresponds to the field-effect transistor 100according to the first exemplary embodiment.

[0064] Identical components of the field-effect transistor 300 accordingto the third exemplary embodiment are provided with the same referencenumerals as the corresponding components of the field-effect transistor100 according to the first exemplary embodiment.

[0065] The field-effect transistor 300 according to the third exemplaryembodiment differs from the field-effect transistor 100 according to thefirst exemplary embodiment in particular in that an electricallyinsulating layer 301 with a high dielectric constant, i.e. with adielectric constant in the range from 1 to 1000, or a ferroelectriclayer 301 is applied to the metal layer 104.

[0066] The layer 301 is applied to the entire surface above the channelregion by means of a CVD process, a sputtering process or a physicalvapour deposition process.

[0067] The layer 301 is fabricated, for example, from BST or SBT.

[0068] The thickness of the layer 301, which is diagrammaticallyindicated by a double arrow 302 in FIG. 3, is from 1 nm to 50 nmaccording to the third exemplary embodiment.

[0069] The first gate electrode 109 is applied to the layer 301.

[0070] In a final step, an insulating separating layer 107 is applied,as in the previous exemplary embodiments, to the element which resultsfrom the preceding steps.

[0071] According to a fourth exemplary embodiment, a second gateelectrode (not shown) is also provided for the arrangement according tothe third exemplary embodiment, this second gate electrode beingelectrically coupled to the first gate electrode 109.

[0072] The following publications are cited in this document:

[0073] [1] R. Müller, Bauelemente der Halbleiterelektronik [Componentsused in Semiconductor Electronics], Springer Verlag, first edition, ISBN3-540-06224-6, PP. 130-157, 1973;

[0074] [2] E. S. Snow et al., A metal/oxide tunnelling transistor,Applied Physics Letters, Vol. 72, No. 23, PP. 3071-3073, June 1998;

[0075] [3] G. Martinez-Arizala et al., Coulomb-glass-like behaviour ofultrathin films of metals, Physical Review B, Vol. 57, No. 2, PP.670-672, January 1998;

[0076] [4] Z. Ovadyahu and M. Pollak, Disorder and Magnetic fieldDependence of Slow Electronic Relaxation, Physical Review Letters, Vol.79, No.3, PP. 459-462, July 1997.

1. Field-effect transistor, having an electrically nonconductivesubstrate, a drain region, a source region, having a channel regionbetween the drain region and the source region, having a gate region, bymeans of which the channel region can be controlled, the channel regionhaving a metal layer.
 2. Field-effect transistor according to claim 1,having a second gate region, by means of which the channel region can becontrolled.
 3. Field-effect transistor according to claim 1 or 2, inwhich the metal layer has one or more layers of metal atoms. 4.Field-effect transistor according to one of claims 1 to 3, in which themetal layer contains at least one of the following metals: platinum,gold, silver, titanium, tantalum, palladium, bismuth, indium, chromium,vanadium, manganese, iron, cobalt, nickel, yttrium, zirconium, niobium,molybdenum, technetium, hafnium, tungsten, or an alloy of at least twoof the abovementioned metals.
 5. Field-effect transistor according toone of claims 1 to 4, in which the separating layer is an electricallyinsulating layer.
 6. Field-effect transistor according to one of claims1 to 5, in which the separating layer is a layer with a high dielectricconstant.
 7. Field-effect transistor according to one of claims 1 to 6,in which the separating layer is a ferroelectric layer.
 8. Field-effecttransistor according to one of claims 1 to 7, in which the drain regionand/or the source region and/or the gate region include(s) metal. 9.Process for fabricating a field-effect transistor, in which a drainregion and a source region are formed on a substrate, in which a metallayer which forms a channel region is applied to the substrate betweenthe drain region and the source region, in which a separating layer isapplied to the metal layer and between the drain region and the sourceregion, in which a gate region is formed on the separating layer, thegate region being separated from the drain region, the source region andthe channel region by the separating layer, in such a manner that thechannel region can be controlled by means of the gate region.